In a process of manufacturing a semiconductor device such as a semiconductor integrated circuit device, a plurality of semiconductor elements (semiconductor chips) are formed on one of the main surfaces of a semiconductor substrate such as a silicon (Si) substrate by applying what is known as wafer processing.
Each semiconductor element includes functional elements, e.g., active elements such as transistors and passive elements such as capacitors, and wiring conductors. The wiring conductors interconnect the functional elements to form a desired electronic circuit.
After formation of the semiconductor elements, the semiconductor substrate is diced along scribe regions to separate the semiconductor elements into individual pieces (singulation).
In order to comply with the recent demand for higher function, faster operation electronic appliances, semiconductor devices mounted in such electronic appliances are desired to achieve higher integration and faster operation.
In other words, functional elements such as active elements and passive elements of semiconductor elements constituting semiconductor devices are increasingly miniaturized to achieve higher integration.
In order to speed up the operation, a material mainly composed of copper (Cu) is being used as a material for wiring layers interconnecting the functional elements, and an insulating material having a low dielectric coefficient (a.k.a. low-k material) is used as a material for dielectric layers (interlayer insulating layers) that insulate between the wiring layers.
However, multilevel wiring structures that use a low-k insulating material as the insulating material between wiring layers, i.e., interlayer insulating material, are susceptible to mechanical damage during dicing and thus prone to cracking and/or delamination.
In other words, when a substrate is diced using a dicing blade, rotation of the dicing blade mechanically damages the low-k insulating material layers and tends to cause cracking and/or delamination.
Cracking and/or delamination of the insulating material layers allows moisture penetration and is thus one of the factors that deteriorate the reliability of semiconductor elements.
In this regard, for example, Japanese Laid-open Patent Publication No. 2007-329396 proposes a structure in which a groove is formed between a scribe region and a region where electronic circuits are formed (hereinafter this region is referred to as “circuit region”). This groove surrounds the circuit region, penetrates a multilevel wiring structure that uses an insulating material having a low dielectric constant (low-k insulating material) as the interlayer insulating material, and is filled with an organic insulating material extending from the circuit region.
This groove substantially extends the path through which moisture penetrates into the circuit region.
Japanese Laid-open Patent Publication Nos. 2008-130880 and 2008-166352 also propose structures similar to the aforementioned patent publication.
The groove formed in a multilevel wiring structure that uses a low-k insulating material as the insulating material between wiring layers, i.e., interlayer insulating material, is formed by laser beam irradiation, for example.
Dicing using a dicing blade is performed at the scribe region at the outer side of the groove, i.e., at the side opposite to the circuit region.
That is, the low-k insulating material layers and the underlying semiconductor substrate of the multilevel wiring structure are subject to mechanical dicing in the scribe region.
Thus, even when the structure disclosed in these patent documents is employed, delamination of the low-k insulating material layers having a relatively narrow width and lying between the grooves and the diced part and/or fracture of the semiconductor substrate under the low-k insulating material layers may occur.
According to the structure disclosed in the patent documents, the organic insulating material filling the groove extends from the region where semiconductor elements are formed.
Thus, moisture may penetrate into the region where the semiconductor elements are formed through the interface between the organic insulating material and the low-k insulating material layers.